...tex2html_comment_mark¹

These views are echoed by many in the FPGA community, for example [7]. Incidentally, the VHDL community agrees, but proposes VHDL as the new unified application/hardware language [11, xiii]. However, the slowness of current VHDL simulators/compilers makes this suggestion untenable.

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... tools.²

Object-oriented techniques prove to be useful (see section 6), but here also standard C++ can be used. Compare the work in [7], which shares our unified modelling goals.

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...tex2html_comment_mark³

Note that the externally-visible behavior in the current-implementation is somewhat different: the first and last loop iterations execute concurrently with the pre-loop and post-loop code, respectively, so that the externally-visible states for the example would be: 1, 3, 6, 10, and 20. See section 4 and figure 6 for details.

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... disallowed.⁴

A more refined, if complex, semantics would translate recursive functions into their synthesizable equivalent by rewriting recursion as loops whenever possible. This strategy suffers from somewhat unpredictable behavior.

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... implementation.⁵

See [10] for information on what an implementation would entail.

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